Improving the power-performance of multicore processors through optimization of lithography and thermal processing

It is generally assumed that achieving a narrow distribution of physical gate length (Lpoly) for the poly conductor layer helps improve power performance metrics of modern integrated circuits. However, in advanced 90 nm technologies, there are other drivers of chip performance. In this paper we show that a global optimization of all variables is necessary to achieve the optimum performance at the lowest leakage. We will also describe how systematic physical gate-length variation can improve core matching in multicore designs.