The resilience wall: Cross-layer solution strategies
Subhasish Mitra, Pradip Bose, et al.
VLSI-TSA 2014
Single event upset (SEU) experimental heavy ion data and modeling results for CMOS, silicon-on-insulator (SOI), 32 nm and 45 nm stacked and DICE latches are presented. Novel data analysis is shown to be important for hardness assurance where Monte Carlo modeling with a realistic heavy ion track structure, along with a new visualization aid (the Angular Dependent Cross-section Distribution, ADCD), allows one to quickly assess the improvements, or limitations, of a particular latch design. It was found to be an effective technique for making SEU predictions for alternative 32 nm SOI latch layouts. © 2011 IEEE.
Subhasish Mitra, Pradip Bose, et al.
VLSI-TSA 2014
Aj Kleinosowski, Ethan H. Cannon, et al.
IEEE TNS
Jonathan A. Pellish, Robert A. Reed, et al.
IEEE TNS
Nathaniel A. Dodds, James R. Schwank, et al.
IEEE TNS