Logic Technology
Designing the next generation of chips to increase performance and improve energy efficiency.
Logic scaling is the pathway to advance semiconductor technology to smaller components, to increase performance or to improve energy efficiency. We achieve logic scaling through advances in chip technology such as new architectures and new materials, driving breakthroughs in transistor and interconnect technology at the atomic scale. Our materials and architectures move the industry forward, to meet the world’s demand for increasingly powerful and energy efficient chips.
For decades, IBM has led the industry in logic scaling technology. We coined the term “Nanosheet” in 2015 and, more recently, unveiled our 2 nanometer node test chip in 2021. From approaching 1 nanometer components to scaling foundational technology, our work in logic technology is accelerating the progress and productivity of the chip industry, in collaboration with a rich ecosystem of partners based in Albany, NY.
Our work
- ExplainerMike Murphy
The path to 1 nanometer chips and beyond
ResearchMike MurphyThe future of computer chips is being built in Albany
Deep DiveMike MurphyVTFET: The revolutionary new chip architecture that could keep Moore’s Law alive for years to come
NewsBrent Anderson and Hemanth Jagannathan5 minute readIntroducing the world's first 2 nm node chip
NewsJulien Frougier and Dechao Guo5 minute readEUV patterning yield breakthrough sets new benchmark for logic scaling
Technical noteNelson Felix and Luciana Meli4 minute read- See more of our work on Logic Technology
Publications
Exploring the Limits of Contact Hole Patterning with High NA EUV Lithography
- Dario Goldfarb
- Zheng Chen
- et al.
- 2026
- SPIE Advanced Lithography + Patterning 2026
Mitigating X‑ray–Induced Damage in CD‑SAXS Metrology of EUV Resists
- Philipp Wieser
- Kevin Yager
- et al.
- 2026
- SPIE Advanced Lithography + Patterning 2026
Block-Level Design Optimization for Sub-100-nm Cell Height Libraries with Stacked Transistor
- Nick Lanzillo
- Jim Mazza
- et al.
- 2025
- IEDM 2025
SiGe Channel for Scaled Gate-All-Around Nanosheet pFET Transistor for Advanced Logic Applications
- Shogo Mochizuki
- Sushant Kumar
- et al.
- 2025
- IEDM 2025
28P L/S Dry Resist Process Flow Co-optimization at Low NA EUV
- Chun-chia Brown Lu
- Saumya Gulati
- et al.
- 2025
- ANS 2025
Dose reduction strategies for low-n PSM absorber using pupil and mask bias optimization at 0.33NA EUV lithography
- Rajiv Sejpal
- Gopal Kenath
- et al.
- 2025
- Photomask Japan 2025
Projects
Platform technology research: innovation and solution creation for leading edge CMOS technology at 2nm node.