Yichen Xu, Baoqi Zhu, et al.
VLSI Technology and Circuits 2026
Background: Continued scaling requires simultaneous reduction of edge-placement error (EPE) and stochastic defectivity at increasingly tight pitches, where photon statistics, resist response, and mask 3D effects constrain manufacturable single-exposure patterning.
Aim: To define a practical roadmap for meeting aggressive EPE targets with single exposure while suppressing stochastic failures by co-optimizing exposure wavelength/NA, resist robustness, and mask format (magnification) for future nodes.
Approach: Using a 14-nm-pitch use case, we analyze the trade-off between photon shot noise (photon count) and aerial-image slope when transitioning from 13.5-nm EUV two-beam imaging to shorter-wavelength (2.5–4.5 nm) three-beam imaging at low NA. We translate this into requirements for resist exposure latitude under aggregate effective-dose variation and assess mask-format scaling as a lever to reduce mask 3D effects and improve pupil uniformity.
Results: Three-beam imaging at 2.5–4.5 nm enables ~2.5× higher ILS than two-beam imaging at 13.5 nm for 14-nm pitch. At equal dose, this ILS gain offsets the √N photon-statistics penalty and yields ~17% lower LER. We propose a resist robustness criterion of ≥±6σ dose‑window coverage (printable dose window across aggregate effective‑dose variation) to suppress stochastic failures. We further motivate larger mask formats enabling increased mask-side magnification (7× on 300 mm or 8× on 12×12 inch substrates), which reduces mask 3D effects, lowers chief-ray angle at the mask into the ~2–3° range with reduced angular spread, and improves pupil amplitude and phase uniformity. The combined strategy supports manufacturable depth-of-focus (≥40 nm) at low NA.
Conclusions: Shorter-wavelength, low-NA three-beam imaging, paired with robust, high-latitude resist processes and higher-magnification mask formats, provides a credible path to single-expose patterning at pitches relevant to IBM’s nanostack era while reducing stochastic defect risk, meeting EPE targets and maintaining manufacturable depth-of-focus.
Yichen Xu, Baoqi Zhu, et al.
VLSI Technology and Circuits 2026
Lin Dong, Steven Hung, et al.
VLSI Technology 2021
Alex Hubbard, Christopher Carr, et al.
SPIE Advanced Lithography + Patterning 2026
Akihiro Horibe, Yoichi Taira, et al.
IEDM 2025