Scaling Single Expose EUV Gate LER Through Source-Resist-Mask Co-optimization
- Gopal Kenath
- Martin Burkhardt
- et al.
- 2026
- SPIE Advanced Lithography + Patterning 2026
Publications
12 results for Indira Seshadri
28P L/S Dry Resist Process Flow Co-optimization at Low NA EUV
- Chun-chia Brown Lu
- Saumya Gulati
- et al.
- 2025
- ANS 2025
Dose reduction strategies for low-n PSM absorber using pupil and mask bias optimization at 0.33NA EUV lithography
- Rajiv Sejpal
- Gopal Kenath
- et al.
- 2025
- Photomask Japan 2025
Evaluating Novel Material Stacks Towards Gate Width Roughness Reduction
- Gopal Kenath
- Martin Burkhardt
- et al.
- 2025
- SPIE Advanced Lithography + Patterning 2025
Accelerating High NA EUV Lithography Insertion for Interconnect Scaling and Beyond: Performance, Cost, and Future Prospects
- Luciana Meli
- Indira Seshadri
- et al.
- 2025
- SPIE Advanced Lithography + Patterning 2025
Dry Resist Characterization Towards Technology Insertion for 28-36P EUV Patterning
- Yasiel Cabrera
- Gopal Kenath
- et al.
- 2025
- SPIE Advanced Lithography + Patterning 2025
Advanced Multi-Vt Enabled by Selective Layer Reductions for 2nm Nanosheet Technology and Beyond
- Ruqiang Bao
- Yusuke Oniki
- et al.
- 2024
- IEDM 2024
EUV patterned gate variation reduction in next generation transistor architectures
- Gopal Kenath
- Martin Burkhardt
- et al.
- 2024
- SPIE Advanced Lithography + Patterning 2024
Scaling opportunities for Gate-All-Around and beyond: A patterning perspective
- Indira Seshadri
- Eric Miller
- et al.
- 2023
- IEDM 2023
Hardware Based Performance Assessment of Vertical-Transport Nanosheet Technology
- Gen Tsutsui
- Seunghyun Song
- et al.
- 2022
- IEDM 2022