M. Hargrove, S.W. Crowder, et al.
IEDM 1998
A leading-edge 0.13 μm generation CMOS technology is presented as a platform for systems on a chip (SOC) applications. A modular triple gate oxide process concept is introduced for the first time to allow the optimization of high performance devices, low leakage devices, and I/O devices independently. Process commonality is also achieved to support deep-trench based embedded DRAM. Seven levels of Cu interconnects integrated with low-k ILD have been developed. With mature KrF 248 nm lithography and optical enhancement techniques, aggressive design rules are achieved to meet the circuit density requirement. A 2.48 μm2 functional ST-SRAM cell is demonstrated.
M. Hargrove, S.W. Crowder, et al.
IEDM 1998
D. Edelstein, J. Heidenreich, et al.
IEDM 1997
N.J. Chou, J. Paraszczak, et al.
Journal of Vacuum Science and Technology A: Vacuum, Surfaces and Films
J.H. Stathis, A. Vayshenker, et al.
VLSI Technology 2000