Latch design techniques for mitigating single event upsets in 65 nm SOI device technology

A.J. KleinOsowski; Ethan H. Cannon; Michael S. Gordon; David F. Heidel; Phil Oldiges; Cristina Plettner; Kenneth P. Rodbell; Ronald D. Rose; Henry H. K. Tang

doi:10.1109/TNS.2007.909707

IEEE TNS

Paper

01 Dec 2007

Latch design techniques for mitigating single event upsets in 65 nm SOI device technology

View publication

Abstract

This paper describes techniques for mitigating single event upsets in master-slave flip-flop latches in 65 nm SOI device technology. Techniques are explained, modeled, and measured with hardware experiments. © 2007 IEEE.

Paper

Single-event-upset critical charge measurements and modeling of 65 nm silicon-on-insulator latches and memory cells

David F. Heidel, Kenneth P. Rodbell, et al.

IEEE TNS

Paper

Flip-flop upsets from single-event-transients in 65 nm clock circuits

Larry Wissel, David F. Heidel, et al.

IEEE TNS

Paper

Giant piezoresistive On/Off ratios in rare-earth chalcogenide thin films enabling nanomechanical switching

Matthew Copel, Marcelo A. Kuroda, et al.

Nano Letters

Conference paper

SRAM ser in 90, 130 and 180 nm bulk and SOI technologies

Ethan H. Cannon, Daniel D. Reinhardt, et al.

IRPS 2004

View all publications

Abstract

Related

Single-event-upset critical charge measurements and modeling of 65 nm silicon-on-insulator latches and memory cells

Flip-flop upsets from single-event-transients in 65 nm clock circuits

Giant piezoresistive On/Off ratios in rare-earth chalcogenide thin films enabling nanomechanical switching

SRAM ser in 90, 130 and 180 nm bulk and SOI technologies