Publications

11 results at VLSI Technology 2011

Scaling of SOI FinFETs down to fin width of 4 nm for the 10nm technology node
- - Josephine Chang
  - Michael A. Guillorn
  - et al.
- 2011
- VLSI Technology 2011
A 0.021 μm² trigate SRAM cell with aggressively scaled gate and contact pitch
- - Michael A. Guillorn
  - Josephine Chang
  - et al.
- 2011
- VLSI Technology 2011
Sub-25nm FinFET with advanced fin formation and short channel effect engineering
- - Tenko Yamashita
  - Veeraraghvan S. Basker
  - et al.
- 2011
- VLSI Technology 2011
Understanding short-term BTI behavior through comprehensive observation of gate-voltage dependence of RTN in highly scaled high-κ / metal-gate pFETs
- - Hiroshi Miki
  - M. Yamaoka
  - et al.
- 2011
- VLSI Technology 2011
A method to maintain phase-change memory pre-coding data retention after high temperature solder bonding process in embedded systems
- - H.L. Lung
  - Matthew Breitwisch
  - et al.
- 2011
- VLSI Technology 2011
Endurance and scaling trends of novel access-devices for multi-layer crosspoint-memory based on mixed-ionic-electronic-conduction (MIEC) materials
- - R.S. Shenoy
  - K. Gopalakrishnan
  - et al.
- 2011
- VLSI Technology 2011
3D integration from the viewpoint of high-end server system design
- - Jeffrey L. Burns
- 2011
- VLSI Technology 2011
ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08μm² SRAM cell
- - Kangguo Cheng
  - A. Khakifirooz
  - et al.
- 2011
- VLSI Technology 2011
Modeling of width-quantization-induced variations in logic FinFETs for 22nm and beyond
- - Chung-Hsun Lin
  - Wilfried Haensch
  - et al.
- 2011
- VLSI Technology 2011
Full metal gate with borderless contact for 14 nm and beyond
- - Soon-Cheon Seo
  - L.F. Edge
  - et al.
- 2011
- VLSI Technology 2011