Degradation of high-κ/metal gate nMOSFETs under ESD-like stress in a 32-nm technology
- Yang Yang
- Robert J. Gauthier
- et al.
- 2011
- IEEE T-DMR
Paper
Publications
19 results for Kiran Chatty
Pulsed gate dielectric breakdown in a 32 nm technology under different ESD stress configurations
- Yang Yang
- Robert Gauthier
- et al.
- 2010
- EOS/ESD 2010
Conference paperCharacterization of high-k/metal gate stack breakdown in the time scale of ESD events
- Yang Yang
- James Di Sarro
- et al.
- 2010
- IRPS 2010
Conference paperESD time-domain characterization of high-k gate dielectric in a 32 nm CMOS technology
- James Di Sarro
- Yang Yang
- et al.
- 2009
- EOS/ESD 2009
Conference paperTechnology scaling of advanced bulk CMOS on-chip ESD protection down to the 32nm node
- Junjun Li
- Kiran Chatty
- et al.
- 2009
- EOS/ESD 2009
Conference paperCapacitance investigation of diode and GGNMOS for ESD protection of high frequency circuits in 45nm SOI CMOS technologies
- Junjun Li
- Souvick Mitra
- et al.
- 2008
- EOS/ESD 2008
Conference paperFailure analysis of I/O with ESD protection devices in advanced CMOS technologies
- Mujahid Muhammad
- Robert Gauthier
- et al.
- 2007
- IPFA 2007
Conference paperCapacitance investigation of diodes and SCRs for ESD protection of high frequency circuits in sub-100nm bulk CMOS technologies
- Junjun Li
- Robert Gauthier
- et al.
- 2007
- EOS/ESD 2007
Conference paperEvaluation of SCR-based ESD protection devices in 90nm and 65nm CMOS technologies
- James Di Sarro
- Kiran Chatty
- et al.
- 2007
- IRPS 2007
Conference paperDesign and characterization of a multi-rc-triggered MOSFET-based power clamp for on-chip ESD protection
- Junjun Li
- Robert Gauthier
- et al.
- 2006
- EOS/ESD 2006
Conference paper