Assessment of structure variation in silicon nanowire FETs and impact on SRAM
- Yi-Bo Liao
- Meng-Hsueh Chiang
- et al.
- 2012
- Microelectronics Journal
Paper
Publications
16 results for Meng-Hsueh Chiang
A high-density SRAM design technique using silicon nanowire FETs
- Yi-Bo Liao
- Meng-Hsueh Chiang
- et al.
- 2011
- LISS 2011
Conference paperVariability study of silicon nanowire FETs
- Yi-Bo Liao
- Meng-Hsueh Chiang
- et al.
- 2011
- NSTI-Nanotech 2011
Conference paperHigh-performance ultra-low power junctionless nanowire FET on SOI substrate in subthreshold logic application
- Chun-Yu Chen
- Jyi-Tsong Lin
- et al.
- 2010
- IEEE International SOI Conference 2010
Conference paperOptimal design and performance assessment of extremely-scaled Si nanowire FET on insulator
- Chun-Yu Chen
- Yi-Bo Liao
- et al.
- 2009
- IEEE International SOI Conference 2009
Conference paperDouble-Gate MOSFETs with aymmetric drain underlap: A device-circuit co-design and optimization perspective for SRAM
- Ashish Goel
- Sumeet Gupta
- et al.
- 2009
- DRC 2009
Conference paperOptimal design of triple-gate devices for high-performance and low-power applications
- Meng-Hsueh Chiang
- Jeng-Nan Lin
- et al.
- 2008
- IEEE Transactions on Electron Devices
PaperAsymmetrical triple-gate FET
- Meng-Hsueh Chiang
- Jeng-Nan Lin
- et al.
- 2007
- SISPAD 2007
Conference paperRandom dopant fluctuation in limited-width FinFET technologies
- Meng-Hsueh Chiang
- Jeng-Nan Lin
- et al.
- 2007
- IEEE Transactions on Electron Devices
PaperDiscrete dopant fluctuation in limited-width FinFETs for VLSI circuit application: A theoretical study
- Meng-Hsueh Chiang
- Jeng-Nan Lin
- et al.
- 2006
- ICICDT 2006
Conference paper