Asymmetrical triple-gate FET

A novel triple-gate MOSFET structure with polysilicon gate process is proposed using asymmetrical (n+/p+) polysilicon gates. CMOS-compatible VT's for high-performance circuit applications can be achieved for both nFET and pFET. The superior subthreshold characteristics and device performance are analyzed by three-dimensional numerical simulations. Comparisons of device properties with the mid-gap metal gate are presented.