POWER8 design methodology innovations for improving productivity and reducing power
- 2014
- CICC 2014
Publications
30 results for Robert Franch
A shorted global clock design for multi-GHz 3D stacked chips
- Liang-Teck Pang
- Phillip J. Restle
- et al.
- 2012
- VLSI Circuits 2012
On-chip timing uncertainty measurements on IBM microprocessors
- R.L. Franch
- P. Restle
- et al.
- 2008
- IEEE ITC 2008
Impact of Self-Heating on Digital SOI and Strained-Silicon CMOS Circuits
- Keith A. Jenkins
- R.L. Franch
- 2003
- IEEE International SOI Conference 2003
The physical design of on-chip interconnections
- Mary Y.L. Wisniewski
- Emmanuel Yashchin
- et al.
- 2003
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Estimating the efficiency of collaborative problem-solving, with applications to chip design
- M.Y.L. Wisniewski
- E. Yashchin
- et al.
- 2003
- IBM J. Res. Dev
A 640-ps, 0.25-μm CMOS, 16 × 64-b three-port register file
- R.L. Franch
- J. Ji
- et al.
- 1997
- IEEE Journal of Solid-State Circuits
A Room Temperature 0.1 µm CMOS on SOI
- Ghavam G. Shahidi
- Carl A. Anderson
- et al.
- 1994
- IEEE Transactions on Electron Devices
A Novel Borderless Contact/Interconnect Technology Using Aluminum Oxide Etch Stop for High Performance SRAM and Logic
- S. Subbanna
- D.L. Harame
- et al.
- 1993
- IEDM 1993
SOI for a 1-Volt CMOS Technology and Application to a 512kb SRAM with 3.5 ns Access Time
- G. Shahidi
- T.H. Ning
- et al.
- 1993
- IEDM 1993