TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip
- Filipp Akopyan
- Jun Sawada
- et al.
- 2015
- IEEE TCADIS
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28 results for Michael P. Beakes
A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology
- Timothy O. Dickson
- Yong Liu
- et al.
- 2015
- IEEE JSSC
A 25Gb/s burst-mode receiver for rapidly reconfigurable optical networks
- Alexander V. Rylyakov
- Jonathan E. Proesel
- et al.
- 2015
- ISSCC 2015
A 3.5pJ/bit 8-tap-feed-forward 8-tap-decision feedback digital equalizer for 16Gb/s I/Os
- Thomas Toifl
- Peter Buchmann
- et al.
- 2014
- ESSCIRC 2014
A 23.5 GHz PLL with an adaptively biased VCO in 32 nm SOI-CMOS
- Jean-Olivier Plouchart
- Mark A. Ferriss
- et al.
- 2013
- IEEE TCAS-I
A 3.2GS/s 4.55b ENOB two-step subranging ADC in 45nm SOI CMOS
- Jean-Olivier Plouchart
- Mihai Sanduleanu
- et al.
- 2012
- CICC 2012
A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS
- Jean-Olivier Plouchart
- Mark A. Ferriss
- et al.
- 2012
- CICC 2012
An 8x 10-Gb/s source-synchronous I/O system based on high-density silicon carrier interconnects
- Timothy O. Dickson
- Yong Liu
- et al.
- 2012
- IEEE Journal of Solid-State Circuits
High-density silicon carrier transmission line design for chip-to-chip interconnects
- Xiaoxiong Gu
- Lavanya Turlapati
- et al.
- 2011
- EPEPS 2011
An 8x10-Gb/s source-synchronous I/O system based on high-density silicon carrier interconnects
- Timothy O. Dickson
- Yong Liu
- et al.
- 2011
- VLSI Circuits 2011