A 22 Gbit/s PAM-4 receiver in 90nm CMOS-SOI technology
Thomas Toifl, Christian Menolfi, et al.
VLSI Circuits 2005
This paper presents a single-chip all-CMOS solution for 4×OC-3c, OC-12, and OC-12c synchronous digital hierarchy/synchronous optical network (SDH/SONET) framing with integrated serial line interfaces. Outstanding features of this chip are clock and data recovery and fulfillment of ITU-T and Bellcore jitter requirements for SDH/SONET systems, as well as the large range of functions offered. These functions include asynchronous transfer mode (ATM) and point-to-point protocol (PPP) support, as well as built-in native SDH/SONET functions such as digital cross-connect, add/drop multiplexing, and automatic protection switching. In addition, the chip is based on a new scalable modular architecture.
Thomas Toifl, Christian Menolfi, et al.
VLSI Circuits 2005
Alexander V. Rylyakov, Jonathan E. Proesel, et al.
ISSCC 2015
Thomas Toifl, Michael Ruegg, et al.
VLSI Circuits 2012
Alexander V. Rylyakov, Jonathan E. Proesel, et al.
IEEE JSSC