Publications

61 results for Peter Buchmann

A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI
- - Sergey V. Rylov
  - Troy Beukema
  - et al.
- 2016
- ISSCC 2016
A 3.6pJ/b 56Gb/s 4-PAM receiver with 6-Bit TI-SAR ADC and quarter-rate speculative 2-tap DFE in 32 nm CMOS
- - Hazar Yueksel
  - Lukas Kull
  - et al.
- 2015
- ESSCIRC 2015
A 16 Gb/s 3.7 mW/Gb/s 8-tap DFE receiver and baud-rate CDR with 31 kppm tracking bandwidth
- - Pier Andrea Francese
  - Thomas Toifl
  - et al.
- 2014
- IEEE JSSC
A 3.5pJ/bit 8-tap-feed-forward 8-tap-decision feedback digital equalizer for 16Gb/s I/Os
- - Thomas Toifl
  - Peter Buchmann
  - et al.
- 2014
- ESSCIRC 2014
A 16 Gb/s receiver with DC wander compensated rail-to-rail AC coupling and passive linear-equalizer in 22 nm CMOS
- - Pier Andrea Francese
  - Thomas Toifl
  - et al.
- 2014
- ESSCIRC 2014
Scalable, efficient ASICS for the square kilometre array: From A/D conversion to central correlation
- - Martin L. Schmatz
  - Rik Jongerius
  - et al.
- 2014
- ICASSP 2014
A deep trench capacitor based 2:1 and 3:2 reconfigurable on-chip switched capacitor DC-DC converter in 32 nm SOI CMOS
- - Toke M. Andersen
  - Florian Krismer
  - et al.
- 2014
- APEC 2014
A sub-ns response on-chip switched-capacitor DC-DC voltage regulator delivering 3.7W/mm² at 90% efficiency using deep-trench capacitors in 32nm SOI CMOS
- - Toke Meyer Andersen
  - Florian Krismer
  - et al.
- 2014
- ISSCC 2014
A 10 Gb/s 8-tap 6b 2-PAM/4-PAM tomlinson-harashima precoding transmitter for future memory-link applications in 22-nm SOI CMOS
- - Marcel Kossel
  - Thomas Toifl
  - et al.
- 2013
- IEEE JSSC
A 16Gb/s 3.7mW/Gb/s 8-tap DFE receiver and baud rate CDR with 30kppm tracking bandwidth
- - Pier Andrea Francese
  - Thomas Toifl
  - et al.
- 2013
- A-SSCC 2013