Karen M. Coperich, Jason Morsey, et al.
IEEE T-MTT
The large number of coupled lines in an interconnect structure is a serious limiting factor in simulating high-speed circuits. A new method is presented for efficient simulation of large interconnects based on transverse partitioning and waveform relaxation techniques. The computational cost of the proposed algorithm grows linearly with the number of coupled lines. In addition, the algorithm is highly suitable for parallel implementation leading to further significant reduction in the computational complexity. © 2006 IEEE.
Karen M. Coperich, Jason Morsey, et al.
IEEE T-MTT
Chung W. Ho, David A. Zein, et al.
IEEE Transactions on Circuits and Systems
Albert E. Ruehli, George Papadopoulos
EMC 1999
Giulio Antonini, Albert E. Ruehli
EMC 2008