C. Wang, S.W. Nam, et al.
IEDM 2013
We demonstrate self-aligned fully-depleted III-V MOSFETs using CMOS-compatible device structures and manufacturable process flows. Processes with good manufacturability and scalability, such as, gate definition and spacer formation using RIE, and formation of self-aligned source/drain extensions (SDE) and self-aligned raised source/drain (RSD), have been established on III-Vs. We demonstrate short-channel devices down to gate length LG = 30 nm. Our best short-channel devices exhibit peak saturation transconductance GMSAT = 1140 μS/μm at LG = 60 nm and supply voltage VDD = 0.5 V. © 2013 IEEE.
C. Wang, S.W. Nam, et al.
IEDM 2013
Kafai Lai, Alan E. Rosenbluth, et al.
SPIE Advanced Lithography 2007
John G. Long, Peter C. Searson, et al.
JES
E. Burstein
Ferroelectrics