FinFET SRAM for high-performance low-power applications
Rajiv V. Joshi, Richard Q. Williams, et al.
ESSDERC/ESSCIRC 2004
This paper presents a new power gating structure with robust data retention capability using only one single double-gate device to provide both power gating switch and virtual supply/ground diode clamp functions. The scheme reduces the transistor count, area, and capacitance of the power gating structure, thus improving circuit performance, power, and leakage. The scheme is compared to the conventional power gating structure via mixed-mode physics-based two-dimensional numerical simulations. Analysis of virtual ground bounce for the proposed scheme is also presented.
Rajiv V. Joshi, Richard Q. Williams, et al.
ESSDERC/ESSCIRC 2004
R. Rodríguez, R.V. Joshi, et al.
SISPAD 2003
R. Puri, C.T. Chuang
ISLPED 1999
T.C. Chen, J.D. Cressler, et al.
VLSI Technology 1989