Conference paper
Effects of gate-to-body tunneling current on PD/SOI CMOS SRAM
R.V. Joshi, C.T. Chuang, et al.
VLSI Technology 2001
A detailed study on the scaling property trench isolation capacitance for advanced high-performance bipolar applications is presented. It is shown that the trench isolation capacitance depends on the trench structure, particularly the trench bottom and the trench fill. The dependence of the trench isolation capacitance on the trench width is then analyzed for various commonly used trench structures. The impact on the scaled-down high-performance ECL circuits is presented. © 1990 IEEE
R.V. Joshi, C.T. Chuang, et al.
VLSI Technology 2001
R. Puri, C.T. Chuang
IEEE International SOI Conference 1998
P.F. Lu, C.T. Chuang
CICC 1992
Satish Kumar, Rajiv V. Joshi, et al.
ICICDT 2007