A. Bette, J.K. DeBrosse, et al.
VLSI Circuits 2003
Testing is a crucial process in the development and production of VLSI memory chips. On-chip test modes not only reduce manufacturing test time, but also allow effective debugging of the technology during the development phase. This paper describes the flexible test modes deployed in our fully functional 256Mb DRAM chip.
A. Bette, J.K. DeBrosse, et al.
VLSI Circuits 2003
G. Wang, K. Cheng, et al.
IEDM 2006
J.A. Mandelman, J. Barth, et al.
IEEE International SOI Conference 1996
R.A. Haring, M.S. Milshtein, et al.
VLSI Circuits 1996