Publications

34 results for Toshiaki Kirihata

Three-Dimensional Dynamic Random Access Memories Using Through-Silicon-Vias
- - Toshiaki Kirihata
  - John Golz
  - et al.
- 2016
- IEEE JESTCS
Oxygen vacancy traps in Hi-K/Metal gate technologies and their potential for embedded memory applications
- - C. Kothandaraman
  - X. Chen
  - et al.
- 2015
- IRPS 2015
Three dimensional dynamic random access memory
- - Toshiaki Kirihata
- 2014
- LTB-3D 2014
Copper-to-dielectric heterogeneous bonding for 3D integration
- - Wei Lin
  - Juntao Li
  - et al.
- 2014
- LTB-3D 2014
A 45 nm SOI embedded DRAM macro for the POWER™ processor 32 MByte on-chip L3 cache
- - John Barth
  - Don Plass
  - et al.
- 2011
- IEEE Journal of Solid-State Circuits
A 0.039um² high performance eDRAM cell based on 32nm high-K/metal SOI technology
- - Nauman Z. Butt
  - Kevin McStay
  - et al.
- 2010
- IEDM 2010
Process-design considerations for three dimensional memory integration
- - S.S. Iyer
  - T. Kirihata
  - et al.
- 2009
- VLSI Technology 2009
A 1 MB cache subsystem prototype with 1.8 ns embedded DRAMs in 45 nm SOI CMOS
- - Peter J. Klim
  - John Barth
  - et al.
- 2009
- IEEE Journal of Solid-State Circuits
An on-chip dual supply charge pump system for 45nm PD SOI eDRAM
- - J.B. Kuang
  - A. Mathews
  - et al.
- 2008
- ESSCIRC 2008
A one MB cache subsystem prototype with 2GHz embedded DRAMs in 45nm SOI CMOS
- - Peter Klim
  - John Barth
  - et al.
- 2008
- VLSI Circuits 2008