Evaluation of In-line SIMS Impact on Device Reliability and Performance

In this paper, possible impacts on production wafers by in-line SIMS, which is designed specifically for in-fab use, are investigated by evaluating the potential contamination and defects arising from ion sputtering. Assessments include planarization effectiveness prior to lithography, electrical tests to evaluate transistor performance, and surface roughness characterization. Craters resulting from sputtering exhibit shallow sidewall angles, allowing for effective filling prior to lithography with no negative impact on subsequent processing. In-line electrical tests showed no performance impact on gate-all-around nanosheet transistors related to sputtering performed after various processing steps through front-end-of-line manufacturing. In addition, surface roughness as a function of sputter direction was evaluated on fully integrated targets, which is critical for understanding depth resolution when performing in-line SIMS on patterned areas. The results demonstrate that in-line SIMS does not impact device reliability or performance and may be implemented as an in-line metrology solution.