Design methodology for a large communication chip

Rolf Clauberg; Peter Buchmann; Andreas Herkersdorf; David J. Webb

doi:10.1109/54.867899

IEEE Design and Test of Computers

Paper

01 Jul 2000

Design methodology for a large communication chip

View publication

Abstract

Smart chip is a large communication chip with standard-based communication interfaces, multiple clock domains, and mixed-signal components for line interfacing. This chip has been developed by focusing mainly on general design aspects.

Paper

Microfields in stroboscopic voltage measurements via electron emisson. II. Effects on electron dynamics

Paper

Single-chip 622-Mb/s SDH/SONET framer, digital cross-connect and add/drop multiplexer solution

Paper

High electron density effects in electron spectroscopies: Consequences for picosecond photoemission and electron-beam sampling

Paper

A 0.94-ps-RMS-Jitter 0.016-mm ² 2.5-GHz Multiphase Generator PLL with 360° Digitally Programmable Phase Shift for 10-Gb/s Serial Links

View all publications

Abstract

Related

Microfields in stroboscopic voltage measurements via electron emisson. II. Effects on electron dynamics

Single-chip 622-Mb/s SDH/SONET framer, digital cross-connect and add/drop multiplexer solution

High electron density effects in electron spectroscopies: Consequences for picosecond photoemission and electron-beam sampling

A 0.94-ps-RMS-Jitter 0.016-mm 2 2.5-GHz Multiphase Generator PLL with 360° Digitally Programmable Phase Shift for 10-Gb/s Serial Links

A 0.94-ps-RMS-Jitter 0.016-mm ² 2.5-GHz Multiphase Generator PLL with 360° Digitally Programmable Phase Shift for 10-Gb/s Serial Links