Design methodology for a large communication chip

Rolf Clauberg; Peter Buchmann; Andreas Herkersdorf; David J. Webb

doi:10.1109/54.867899

IEEE Design and Test of Computers

Paper

01 Jul 2000

Design methodology for a large communication chip

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Abstract

Smart chip is a large communication chip with standard-based communication interfaces, multiple clock domains, and mixed-signal components for line interfacing. This chip has been developed by focusing mainly on general design aspects.

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Electrical and optical transceivers for short-range data communication, fabricated in VLSI 90-nm bulk and SOI CMOS technology

Technologies and building blocks for fast packet forwarding

A T-coil-enhanced 8.5 Gb/s high-swing SST transmitter in 65 nm bulk CMOS with &lt; 16 dB return loss over 10 GHz bandwidth

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A T-coil-enhanced 8.5 Gb/s high-swing SST transmitter in 65 nm bulk CMOS with < 16 dB return loss over 10 GHz bandwidth