Interpreting Data from Scanned Tables
Waleed Farrukh, Antonio Foncubierta-Rodriguez, et al.
GREC 2017
We present a design methodology for a modular network processor architecture that leads to a balanced, service-defined mix between programmable processor cores, configurable hardware assists, and specialized coprocessors. Whereas the processor cores address the flexibility and extendibility needs of the networking market, the hardware components offload the processors, or even allow them to be bypassed for certain network processor-typical tasks to optimize chip area, performance, and power efficiency. We describe the rationale behind the selected functional partitioning in hardware and software components and discuss the challenges of designing the hardware components, and of organizing and integrating the programmable cores. We quantify our approach with a performance evaluation of the overall system. © 2003 Published by Elsevier Science B.V.
Waleed Farrukh, Antonio Foncubierta-Rodriguez, et al.
GREC 2017
Erwan Zerhouni, David Lanyi, et al.
ISBI 2017
David E. Taylor, Andreas Herkersdorf, et al.
IEEE/ACM Transactions on Networking
Gero Dittmann
DATE 2004