On-chip timing uncertainty measurements on IBM microprocessors
R.L. Franch, P. Restle, et al.
IEEE ITC 2008
This paper describes a test pattern for testing DRAM cell data retention that differs from conventional retention time tests. The test pattern is applicable to non-VDD bitline precharge designs, and is specifically designed to test for worst-case subthreshold leakage through the cell access device by holding bit lines in their latched position for extended periods. This action stresses the cell access devices with the worst-case VDSacross them. The reasons to perform this test on a DRAM are reviewed, its advantages over standard retention time tests are described, and its ability to differentiate access device leakage from isolation leakage is discussed. Measured results on a 1-Mb chip are shown, illustrating the test pattern’s effectiveness in screening subthreshold leakage. © 1992 IEEE
R.L. Franch, P. Restle, et al.
IEEE ITC 2008
R.L. Franch, J. Ji, et al.
IEEE Journal of Solid-State Circuits
S.D. Posluszny, Naoaki Aoki, et al.
DAC 2000
O. Takahashi, S. Dhong, et al.
ISSCC 2000