Conference paper
A 19gb/s 38mW 1-tap speculative DFE receiver in 90nm CMOS
Didem Z. Turker, Alexander Rylyakov, et al.
VLSI Circuits 2009
A master-slave latch and companion 1:2, 1:4 and 1:8 static frequency dividers fabricated in 120GHz fT SiGe operate at 51GHz, while drawing 30 mA per latch (780mA total, with input-output buffers) from a -5.2V power supply. At 40Gb/s (40GHz clock) latch operates error-free (BER better than 10-14, 231-1 PRBS) with 152° data-clock phase margin. The directly observed width of the metastability zone of the latch is 1.2ps.
Didem Z. Turker, Alexander Rylyakov, et al.
VLSI Circuits 2009
Jean-Olivier Plouchart, Mark A. Ferriss, et al.
IEEE TCAS-I
Alexander Rylyakov, Thomas Zwick
IEEE Journal of Solid-State Circuits
Ekaterina Laskin, Alexander Rylyakov
SiRF 2009