Model-to-hardware correlations in the design of a 50Gb/s package
Lei Shan, Mounir Meghelli, et al.
ECTC 2003
A static frequency divider designed in a 210-GHz fT, 0.13-μm SiGe bipolar technology is reported. At a -5.5-V power supply, the circuit consumes 44 mA per latch (140 mA total for the chip, with input-output stages). With single-ended sine wave clock input, the divider is operational from 7.5 to 91.6 GHz. Differential clocking under the same conditions extends the frequency range to 96.6 GHz. At -5.0 V and 100 mA total current (28 mA per latch), the divider operates from 2 to 85.2 GHz (single-ended sine wave input).
Lei Shan, Mounir Meghelli, et al.
ECTC 2003
Hayun Chung, Alexander Rylyakov, et al.
VLSI Circuits 2009
Solomon Assefa, William M. J. Green, et al.
URSI GASS 2011
Jose Tierno, Alexander Rylyakov, et al.
Digest of Technical Papers - IEEE International Solid-State Circuits Conference