A timing analysis algorithm for circuits with levelsensitive latches
- Jin Fuw Lee
- Donald T. Tang
- et al.
- 1996
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Paper
Publications
23 results for D.T. Tang
Timing analysis algorithm for circuits with level-sensitive latches
- Jin-Fuw Lee
- D.T. Tang
- et al.
- 1996
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
PaperAlgorithm for incremental timing analysis
- Jin-Fuw Lee
- D.T. Tang
- 1995
- DAC 1995
Conference paperTiming analysis algorithm for circuits with level-sensitive latches
- Jin-Fuw Lee
- D.T. Tang
- et al.
- 1994
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
PaperHIMALAYAS - a hierarchical compaction system with a minimized constraint set
- Jin-Fuw Lee
- D.T. Tang
- 1992
- ICCAD 1992
Conference paperA Hierarchical Global Wiring Algorithm for Custom Chip Design
- W.K. Luk
- Paolo Sipala
- et al.
- 1987
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
PaperVLSI Layout Compaction with Grid and Mixed Constraints
- Jin-Fuw Lee
- Donald T. Tang
- 1987
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
PaperON VLSI LAYOUT COMPACTION WITH MIXED GRID AND EDGE CONSTRAINTS.
- Jin-Fuw Lee
- D.T. Tang
- 1985
- ICCD 1985
Conference paperHierarchical global wiring for custom chip design
- W.K. Luk
- D.T. Tang
- et al.
- 1986
- DAC 1986
Conference paperLogic Test Pattern Generation Using Linear Codes
- Donald T. Tang
- Chin-Long Chen
- 1984
- IEEE TC
Paper