Gate stack resistance and limits to CMOS logic performance
- Richard A. Wachnik
- Sungjae Lee
- et al.
- 2014
- IEEE TCAS-I
Paper
Publications
9 results for Christopher S. Putnam
Gate stack resistance and limits to CMOS logic performance
- Richard A. Wachnik
- S. Lee
- et al.
- 2013
- CICC 2013
Conference paperEfficient and accurate schematic transistor model of FinFET parasitic elements
- Ning Lu
- Terence B. Hook
- et al.
- 2013
- IEEE Electron Device Letters
PaperAn efficient and accurate schematic transistor model of FinFET parasitic elements
- Ning Lu
- Terence B. Hook
- et al.
- 2013
- NSTI-Nanotech 2013
Conference paperAdvanced modeling and optimization of high performance 32nm HKMG SOI CMOS for RF/analog SoC applications
- Sungjae Lee
- J. Johnson
- et al.
- 2012
- VLSI Technology 2012
Conference paperCharacterization and modeling of metal finger capacitors
- Ning Lu
- Roger Booth
- et al.
- 2011
- NSTI-Nanotech 2011
Conference paperDesign and characterization of a multi-rc-triggered MOSFET-based power clamp for on-chip ESD protection
- Junjun Li
- Robert Gauthier
- et al.
- 2006
- EOS/ESD 2006
Conference paperPMOSFET-based ESD protection in 65nm bulk CMOS technology for improved external latchup robustness
- Junjun Li
- Robert Gauthier
- et al.
- 2005
- EOS/ESD 2005
Conference paperElectrostatic discharge induced oxide breakdown characterization in a 0.1 μm CMOS technology
- A. Salman
- R. Gauthier
- et al.
- 2002
- IRPS 2002
Conference paper