A Resistance Drift Compensation Scheme to Reduce MLC PCM Raw BER by Over 100× for Storage Class Memory Applications
- Win-San Khwa
- Meng-Fan Chang
- et al.
- 2017
- IEEE JSSC
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81 results for Matthew BrightSky
Training a Probabilistic Graphical Model with Resistive Switching Electronic Synapses
- Sukru Burc Eryilmaz
- Emre Neftci
- et al.
- 2016
- IEEE T-ED
Investigation of phase change memory confined cell endurance using transmission electron microscopy (TEM)
- Yu Zhu
- Sangbum Kim
- et al.
- 2016
- ISTFA 2016
A Retention-Aware multilevel cell phase change memory program evaluation metric
- Win-San Khwa
- Meng-Fan Chang
- et al.
- 2016
- IEEE Electron Device Letters
A Phase Change Memory Cell With Metal Nitride Liner as a Resistance Stabilizer to Reduce Read Current Noise for MLC Optimization
- Sangbum Kim
- Norma Sosa
- et al.
- 2016
- IEEE T-ED
A Double-Data-Rate 2 (DDR2) Interface Phase-Change Memory with 533MB/s Read-Write Data Rate and 37.5ns Access Latency for Memory-Type Storage Class Memory Applications
- H. Lung
- C. Miller
- et al.
- 2016
- IMW 2016
Recent Progress in Phase-Change Memory Technology
- Geoffrey W. Burr
- Matthew BrightSky
- et al.
- 2016
- IEEE JESTCS
A resistance-drift compensation scheme to reduce MLC PCM raw BER by over 100× for storage-class memory applications
- Win-San Khwa
- Meng-Fan Chang
- et al.
- 2016
- ISSCC 2016
Greater than 2-bits/cell MLC storage for ultra high density phase change memory using a novel sensing scheme
- Jau-Yi Wu
- Win-San Khwa
- et al.
- 2015
- VLSI Technology 2015
A novel self-converging write scheme for 2-bits/cell phase change memory for Storage Class Memory (SCM) application
- W. Chien
- Yung-Han Ho
- et al.
- 2015
- VLSI Technology 2015