Publications

12 results for J. Pille

IBM POWER8 circuit design and energy optimization
- - Victor Zyuban
  - Joshua Friedrich
  - et al.
- 2015
- IBM J. Res. Dev
The 12-core POWER8™ processor with 7.6 Tb/s IO bandwidth, integrated voltage regulation, and resonant clocking
- - Eric J. Fluhr
  - Steve Baumgartner
  - et al.
- 2015
- IEEE JSSC
POWER8^TM: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth
- - Eric J. Fluhr
  - Joshua Friedrich
  - et al.
- 2014
- ISSCC 2014
IBM POWER7 processor circuit design
- - Dieter Wendel
  - John Barth
  - et al.
- 2011
- IBM J. Res. Dev
POWER7™, a highly parallel, scalable multi-core high end server processor
- - Dieter F. Wendel
  - Ron Kalla
  - et al.
- 2011
- IEEE Journal of Solid-State Circuits
A 32nm 0.5V-supply dual-read 6T SRAM
- - Jente B. Kuang
  - J. Schaub
  - et al.
- 2010
- CICC 2010
Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI
- - Brian Flachs
  - Shigehiro Asano
  - et al.
- 2007
- IBM J. Res. Dev
The design and implementation of a low-overhead supply-gated SRAM
- - J.B. Kuang
  - Hung Ngo
  - et al.
- 2006
- ESSCIRC 2006
Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor
- - Dac Pham
  - Hans-Werner Anderson
  - et al.
- 2006
- ASP-DAC 2006
Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor
- - D.C. Pham
  - T. Aipperspach
  - et al.
- 2006
- IEEE Journal of Solid-State Circuits