A 6+ Ghz 128Kb Multi-Port L1 Cache Using Ground Rule Clean 10T Bitcells in 5Nm Technology
- Rajiv Joshi
- John Davis
- et al.
- 2025
- VLSI Technology and Circuits 2025
Conference paper
Publications
13 results for J. Pille
IBM POWER8 circuit design and energy optimization
- Victor Zyuban
- Joshua Friedrich
- et al.
- 2015
- IBM J. Res. Dev
PaperThe 12-core POWER8™ processor with 7.6 Tb/s IO bandwidth, integrated voltage regulation, and resonant clocking
- Eric J. Fluhr
- Steve Baumgartner
- et al.
- 2015
- IEEE JSSC
PaperPOWER8TM: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth
- Eric J. Fluhr
- Joshua Friedrich
- et al.
- 2014
- ISSCC 2014
Conference paperIBM POWER7 processor circuit design
- Dieter Wendel
- John Barth
- et al.
- 2011
- IBM J. Res. Dev
PaperPOWER7™, a highly parallel, scalable multi-core high end server processor
- Dieter F. Wendel
- Ron Kalla
- et al.
- 2011
- IEEE Journal of Solid-State Circuits
PaperA 32nm 0.5V-supply dual-read 6T SRAM
- Jente B. Kuang
- J. Schaub
- et al.
- 2010
- CICC 2010
Conference paperMicroarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI
- Brian Flachs
- Shigehiro Asano
- et al.
- 2007
- IBM J. Res. Dev
PaperThe design and implementation of a low-overhead supply-gated SRAM
- J.B. Kuang
- Hung Ngo
- et al.
- 2006
- ESSCIRC 2006
Conference paperKey features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor
- Dac Pham
- Hans-Werner Anderson
- et al.
- 2006
- ASP-DAC 2006
Conference paper