A 2.6mW 370MHz-to-2.5GHz open-loop quadrature clock generator
Kyu-Hyoun Kim, Paul W. Coteus, et al.
ISSCC 2008
The 12-core 649mm2 POWER8™ leverages IBM's 22nm eDRAM SOI technology [1], and microarchitectural enhancements to deliver up to 2.5× the socket performance [2] of its 32nm predecessor, POWER7+™ [3]. POWER8 contains 4.2B transistors and 31.5μF of deep-trench decoupling capacitance. Three thin-oxide transistor Vts are used for power/performance tuning, and thick-oxide transistors enable high-voltage I/O and analog designs. The 15-layer BEOL contains 5-80nm, 2-144nm, 3-288nm, and 3-640nm pitch layers for low-latency communication as well as 2-2400nm ultra-thick-metal (UTM) pitch layers for low-resistance distribution of power and clocks. © 2014 IEEE.
Kyu-Hyoun Kim, Paul W. Coteus, et al.
ISSCC 2008
Joachim Clabes, Joshua Friedrich, et al.
ISSCC 2003
Matthew M. Ziegler, Victor V. Zyuban, et al.
ISLPED 2009
Joachim Clabes, Joshua Friedrich, et al.
DAC 2004