Publications

16 results for Kevin McStay

Transistor Matching and Fin Angle Variation in FinFET Technology
- - Samarth Agarwal
  - Terence B. Hook
  - et al.
- 2015
- IEEE T-ED
High performance 14nm SOI FinFET CMOS technology with 0.0174μm² embedded DRAM and 15 levels of Cu metallization
- - C.-H.C-H. Lin
  - Brian Greene
  - et al.
- 2014
- IEDM 2014
Deposited ALD SiO₂ high-k/metal gate interface for high voltage analog and I/O devices on next generation alternative channels and FINFET device structures
- - S. Siddiqui
  - M.M. Chowdhury
  - et al.
- 2013
- ECS Meeting 2013
Revisiting the impact on sub-threshold regions in uniaxially-strained FETs
- - M.H. Na
  - K. Mcstay
  - et al.
- 2013
- CSTIC 2013
Performance analysis and modeling of deep trench decoupling capacitor for 32 nm high-performance SOI processors and beyond
- - Balaji Jayaraman
  - Sneha Gupta
  - et al.
- 2012
- ICICDT 2012
A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications
- - S. Krishnan
  - U. Kwon
  - et al.
- 2011
- IEDM 2011
Characterization of novel TiN/HfO₂ metal insulator semiconductor stack for 32nm eDRAM
- - Puneet Goyal
  - Sneha Gupta
  - et al.
- 2010
- IEEE International SOI Conference 2010
A 0.039um² high performance eDRAM cell based on 32nm high-K/metal SOI technology
- - Nauman Z. Butt
  - Kevin McStay
  - et al.
- 2010
- IEDM 2010
Scaling deep trench based eDRAM on SOI to 32nm and beyond
- - G. Wang
  - D. Anand
  - et al.
- 2009
- IEDM 2009
High performance 32nm SOI CMOS with high-k/metal gate and 0.149μm ² SRAM and ultra low-k back end with eleven levels of copper
- - B. Greene
  - Q. Liang
  - et al.
- 2009
- VLSI Technology 2009