Identification and sensitivity analysis of a correlated ground rule system (design arc)
- Eric Eastman
- Dureseti Chidambarrao
- et al.
- 2017
- SPIE Advanced Lithography 2017
Conference paper
Publications
23 results for Werner Rausch
An Analytical Metal Resistance Model and Its Application for Sub-22-nm Metal-Gate CMOS
- X. Miao
- Ruqiang Bao
- et al.
- 2015
- IEEE Electron Device Letters
PaperImpact of lateral asymmetric channel doping on 45-nm-technology N-Type SOI MOSFETs
- Hasan M. Nayfeh
- Nivo Rovedo
- et al.
- 2009
- IEEE Transactions on Electron Devices
PaperSOI series MOSFET for embedded high voltage applications and soft-error immunity
- Jin Cai
- Tak Ning
- et al.
- 2008
- IEEE International SOI Conference 2008
Conference paperHigh performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography
- S. Narasimha
- K. Onishi
- et al.
- 2006
- IEDM 2006
Conference paperBody voltage and history effect sensitivity to key device parameters in 90nm PD-SOI
- S. Kawanaka
- M.B. Ketchen
- et al.
- 2004
- IEEE International SOI Conference 2004
Conference paperA high performance 90 nm SOI technology with 0.992 μm2 6T-SRAM cell
- Mukesh Khare
- S. Ku
- et al.
- 2002
- IEDM 2002
Conference paperDesign of a high performance PD SOI for the 0.18 μm technology generation
- M. Sherony
- S.-H. Lo
- et al.
- 2000
- ICM 2000
Conference paper0.22 μm CMOS-SOI technology with a Cu BEOL
- A. Ajmera
- J. Sleight
- et al.
- 1999
- VLSI Technology 1999
Conference paperElectrostatic discharge protection in silicon-on-insulator technology
- S. Voldman
- D. Hui
- et al.
- 1999
- IEEE International SOI Conference 1999
Conference paper