Marco Bellini, Bongim Jun, et al.
IEEE TNS
We demonstrate a simple and novel scheme to achieve high drain breakdown voltage (BV) in a high-speed silicon-on-insulator (SOI) logic technology. In an SOI device with two FETs in series, the common floating node provides a negative feedback that limits the increase of avalanche current. This unique property of SOI provides a way to enhance the breakdown voltage by simply adding more devices in series. Data from 45nm SOI technology show BV>6.5V for two-NFET in series, and BV>10V for three and four-FET in series. Other benefits of SOI series device include >300x reduction in stand-by leakage current and soft-error immunity as compared to a single SOI device. Our result suggests the prospect of integrating high-voltage functions on SOI-based technologies with little or no additional cost. ©2008 IEEE.
Marco Bellini, Bongim Jun, et al.
IEEE TNS
Qinghuang Lin, Chuck Black, et al.
Microlithography 2003
Jin Cai, Amlan Majumdar, et al.
IEDM 2007
Marco Bellini, Tianbing Chen, et al.
BCTM 2006