Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor
- D.C. Pham
- T. Aipperspach
- et al.
- 2006
- IEEE Journal of Solid-State Circuits
Paper
Publications
131 results for J. Warnock
The design and implementation of a first-generation CELL Processor
- D.C. Pham
- S. Asano
- et al.
- 2005
- ISSCC 2005
Conference paperThe design and implementation of a first-generation CELL processor
- D.C. Pham
- S. Asano
- et al.
- 2005
- ISSCC 2005
Conference paperThe design methodology and implementation of a first-generation CELL processor: A multi-core SoC
- D.C. Pham
- E. Behnen
- et al.
- 2005
- CICC 2005
Conference paperThe design and implementation of double-precision multiplier in a first-generation CELL processor
- J.B. Kuang
- T.C. Buchholtz
- et al.
- 2005
- ICICDT 2005
Conference paperThe design and implementation of a first-generation CELL processor - A multi-core SoC
- D.C. Pham
- S. Asano
- et al.
- 2005
- ICICDT 2005
Conference paperCircuit design issues for the POWER4 chip
- J. Warnock
- 2003
- VLSI-TSA 2003
Conference paperThe circuit and physical design of the POWER4 microprocessor
- J. Warnock
- J. Keaty
- et al.
- 2002
- IBM J. Res. Dev
PaperType-I and Type-II interband transitions in CdSe/ZnTe quantum well structures
- J. Haetty
- E.H. Lee
- et al.
- 1998
- Solid State Communications
PaperHigh performance CMOS circuit techniques for the G-4 S/390 microprocessor
- J. Warnock
- L. Sigal
- et al.
- 1997
- ICCD 1997
Conference paper