CMOS Scaling for High Performance and Low Power—The Next Ten Years
- Bijan Davari
- Robert H. Dennard
- et al.
- 1995
- Proceedings of the IEEE
Paper
Publications
80 results for Robert Dennard
CMOS scaling in the 0.1-μm, 1.X-volt regime for high-performance applications
- G. Shahidi
- J. Warnock
- et al.
- 1995
- IBM J. Res. Dev
PaperCMOS technology for low voltage/low power applications
- B. Davari
- R.H. Dennard
- et al.
- 1994
- CICC 1994
Conference paperA Room Temperature 0.1 µm CMOS on SOI
- Ghavam G. Shahidi
- Carl A. Anderson
- et al.
- 1994
- IEEE Transactions on Electron Devices
PaperSOI for a 1-Volt CMOS Technology and Application to a 512kb SRAM with 3.5 ns Access Time
- G. Shahidi
- T.H. Ning
- et al.
- 1993
- IEDM 1993
Conference paperA room temperature 0.1 μm CMOS on SOI
- G. Shahidi
- C. Blair
- et al.
- 1993
- VLSI Technology 1993
Conference paperDesign and Characterization of a CMOS Off-Chip Driver/Receiver with Reduced Power-Supply Disturbance
- Hussein I. Hanafi
- Robert H. Dennard
- et al.
- 1992
- IEEE Journal of Solid-State Circuits
PaperA 4-Mb Low-Temperature DRAM
- Rick L. Mohler
- Christopher W. Long
- et al.
- 1991
- IEEE Journal of Solid-State Circuits
PaperPower-supply considerations for future scaled CMOS systems
- R.H. Dennard
- 1989
- VLSI-TSA 1989
Conference paperA high performance liquid-nitrogen CMOS SRAM technology
- J.Y.-C. Sun
- S. Klepner
- et al.
- 1988
- ESSDERC 1988
Conference paper