Publications

20 results for Anthony Chou

Optimization of 3nm High Performance Nanosheet Technology for 77 K Operation
- - Julien Frougier
  - Ruqiang Bao
  - et al.
- 2025
- GOMACTech 2025
Advanced Multi-Vt Enabled by Selective Layer Reductions for 2nm Nanosheet Technology and Beyond
- - Ruqiang Bao
  - Yusuke Oniki
  - et al.
- 2024
- IEDM 2024
2^nd Generation dual-channel optimization with cSiGe for 22nm HP technology and beyond
- - C. Ortolland
  - Daniel Jaeger
  - et al.
- 2013
- IEDM 2013
Deposited ALD SiO₂ high-k/metal gate interface for high voltage analog and I/O devices on next generation alternative channels and FINFET device structures
- - S. Siddiqui
  - M.M. Chowdhury
  - et al.
- 2013
- ECS Meeting 2013
Experimental analysis and modeling of self heating effect in dielectric isolated planar and fin devices
- - S. Lee
  - Richard A. Wachnik
  - et al.
- 2013
- VLSI Technology 2013
Advanced modeling and optimization of high performance 32nm HKMG SOI CMOS for RF/analog SoC applications
- - Sungjae Lee
  - J. Johnson
  - et al.
- 2012
- VLSI Technology 2012
Chip-level power-performance optimization through thermally-driven across-chip variation (ACV) reduction
- - X. Yu
  - Oleg Gluschenkov
  - et al.
- 2011
- IEDM 2011
SOI series MOSFET for embedded high voltage applications and soft-error immunity
- - Jin Cai
  - Tak Ning
  - et al.
- 2008
- IEEE International SOI Conference 2008
High performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography
- - S. Narasimha
  - K. Onishi
  - et al.
- 2006
- IEDM 2006
Hybrid-orientation technology (HOT): Opportunities and challenges
- - Min Yang
  - Victor W.C. Chan
  - et al.
- 2006
- IEEE Transactions on Electron Devices