Sub-10-9 Ω-cm2 n-Type Contact Resistivity for FinFET Technology
- Hiroaki Niimi
- Zuoguang Liu
- et al.
- 2016
- IEEE Electron Device Letters
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75 results for Huiming Bu
Aggressively scaled strained-silicon-on-insulator undoped-body High-κ/Metal-Gate nFinFETs for high-performance logic applications
- Kingsuk Maitra
- Ali Khakifirooz
- et al.
- 2011
- IEEE Electron Device Letters
High-performance partially depleted SOI PFETs with in situ doped sige raised source/drain and implant-free extension
- Ali Khakifirooz
- Kangguo Cheng
- et al.
- 2011
- IEEE Electron Device Letters
Extraction of effective oxide thickness for SOI FINFETs with high-κ/Metal gates using the body effect
- Sujata Paul
- Frank Yeh
- et al.
- 2010
- IEEE Electron Device Letters
Highly Selective SiGe Dry Etch Process for the Enablement of Stacked Nanosheet Gate-All-Around Transistors
- Curtis Durfee
- Subhadeep Kal
- et al.
- 2021
- ECS Meeting 2021
Challenges and Opportunities for Stacked Transistor: DTCO and Device
- J. Wang
- S.D. Suk
- et al.
- 2021
- VLSI Technology 2021
Parasitic Resistance Reduction for Aggressively Scaled Stacked Nanosheet Transistors
- Su-Chen Fan
- Ruilong Xie
- et al.
- 2020
- IITC 2020
Selective Enablement of Dual Dipoles for near Bandedge Multi-Vt Solution in High Performance FinFET and Nanosheet Technologies
- Ruqiang Bao
- K. Watanabe
- et al.
- 2020
- VLSI Technology 2020
Self-Allancd Gate Contact (SAGC) for CMOS technology scaling beyond 7nm
- Ruilong Xie
- Chanro Park
- et al.
- 2019
- VLSI Technology 2019
Gate-Cut-Last in RMG to Enable Gate Extension Scaling and Parasitic Capacitance Reduction
- A. Greene
- Huimei Zhou
- et al.
- 2019
- VLSI Technology 2019