Modeling and simulation of transistor performance shift under pattern-dependent RTA process
- Yun Ye
- Frank Liu
- et al.
- 2009
- SPIE Advanced Lithography 2009
Publications
15 results for Yu Cao
Rigorous extraction of process variations for 65-nm CMOS design
- Wei Zhao
- Frank Liu
- et al.
- 2009
- IEEE Trans Semicond Manuf
Fast statistical circuit analysis with finite-point based transistor model
- Min Chen
- Wei Zhao
- et al.
- 2007
- DATE 2007
Loop-based interconnect modeling and optimization approach for multigigahertz clock network design
- Xuejue Huang
- Phillip Restle
- et al.
- 2003
- IEEE Journal of Solid-State Circuits
Loop-based interconnect modeling and optimization approach for multi-GHz clock network design
- Xuejue Huang
- Phillip Restle
- et al.
- 2002
- Proceedings of the Custom Integrated Circuits Conference