Modeling and simulation of transistor performance shift under pattern-dependent RTA process

Rapid-thermal annealing (RTA) is widely used in scaled CMOS fabrication in order to achieve ultra-shallow junction. However, recent results report systematic threshold voltage (V th) change and increased device variation due to the RTA process [1][2]. The amount of such changes further depends on layout pattern density. In this work, a suite of thermal/TCAD simulation and compact models to accurately predict the change of transistor parameters is developed. The modeling results are validated with published silicon data, improving design predictability with advanced manufacturing process. © 2009 SPIE.