A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing
- Bodhisatwa Sadhu
- Mark A. Ferriss
- et al.
- 2013
- IEEE JSSC
Paper
Publications
67 results for Bodhisatwa Sadhu
An integral path self-calibration scheme for a dual-loop PLL
- Mark Ferriss
- Jean-Olivier Plouchart
- et al.
- 2013
- IEEE JSSC
PaperA 23.5 GHz PLL with an adaptively biased VCO in 32 nm SOI-CMOS
- Jean-Olivier Plouchart
- Mark A. Ferriss
- et al.
- 2013
- IEEE TCAS-I
PaperMulti-beam spatio-spectral beamforming receiver for wideband phased arrays
- Sachin Kalia
- Satwik A. Patnaik
- et al.
- 2013
- IEEE TCAS-I
PaperA 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS
- Jean-Olivier Plouchart
- Mark A. Ferriss
- et al.
- 2012
- CICC 2012
Conference paperAn integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS
- Mark Ferriss
- Jean-Olivier Plouchart
- et al.
- 2012
- VLSI Circuits 2012
Conference paperA 21.8-27.5GHz PLL in 32nm SOI using G m linearization to achieve -130dBc/Hz phase noise at 10MHz offset from a 22GHz carrier
- Bodhisatwa Sadhu
- Mark A. Ferriss
- et al.
- 2012
- RFIC 2012
Conference paper