A sub-600-mV, fluctuation tolerant 65-nm CMOS SRAM array with dynamic cell biasing
- Azeez J. Bhavnagarwala
- Stephen Kosonocky
- et al.
- 2008
- IEEE Journal of Solid-State Circuits
Paper
Publications
11 results for Azeez Bhavnagarwala
A sub-600mV, fluctuation tolerant 65nm CMOS SRAM array with dynamic cell biasing
- Azeez Bhavnagarwala
- Stephen Kosonocky
- et al.
- 2007
- VLSI Circuits 2007
Conference paperScalability options for future SRAM memories
- Stephen V. Kosonocky
- Azeez Bhavnagarwala
- et al.
- 2006
- ICSICT 2006
Conference paperFluctuation limits & scaling opportunities for CMOS SRAM cells
- Azeez Bhavnagarwala
- Stephen Kosonocky
- et al.
- 2005
- IEDM 2005
Conference paperA transregional CMOS SRAM with single, logic V DD and dynamic power rails
- Azeez J. Bhavnagarwala
- Stephen V. Kosonocky
- et al.
- 2004
- VLSI Circuits 2004
Conference paperA Pico-Joule Class, 1 GHz, 32 KByte × 64b DSP SRAM with Self Reverse Bias
- Azeez J. Bhavnagarwala
- Stephen V. Kosonocky
- et al.
- 2003
- VLSI Circuits 2003
Conference paperLow-power circuits and technology for wireless digital systems
- Stephen V. Kosonocky
- Azeez J. Bhavnagarwala
- et al.
- 2003
- IBM J. Res. Dev
ReviewThe impact of gate-oxide breakdown SRAM stability
- R. Rodríguez
- J.H. Stathis
- et al.
- 2002
- IEEE Electron Device Letters
PaperAnalysis of the effect of the gate oxide breakdown on SRAM stability
- R. Rodríguez
- J.H. Stathis
- et al.
- 2002
- Microelectronics Reliability
Conference paperNovel circuits to improve SRAM performance in PD/SOI technology
- R.V. Joshi
- A.J. Bhavnagarwala
- et al.
- 2001
- IEEE International SOI Conference 2001
Conference paper