OpenCAPI memory interface signal integrity study for high-speed DDR5 differential DIMM channel with standard loss FR-4 material and SNIA SFF-TA-1002 connector
- Biao Cai
- Jose Hejase
- et al.
- 2019
- ECTC 2019
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23 results for Daniel Dreps
2.1 Summit and Sierra: Designing AI/HPC Supercomputers
- James A. Kahle
- Jaime Moreno
- et al.
- 2019
- ISSCC 2019
ConTutto - a novel FPGA-based prototyping platform enabling innovation in the memory subsystem of a server class processor
- Bharat Sukhwani
- Thomas Roewer
- et al.
- 2017
- MICRO 2017
4.1 22nm Next-generation IBM System z microprocessor
- J. Warnock
- Brian Curran
- et al.
- 2015
- ISSCC 2015
The 12-core POWER8™ processor with 7.6 Tb/s IO bandwidth, integrated voltage regulation, and resonant clocking
- Eric J. Fluhr
- Steve Baumgartner
- et al.
- 2015
- IEEE JSSC
IBM POWER8 circuit design and energy optimization
- Victor Zyuban
- Joshua Friedrich
- et al.
- 2015
- IBM J. Res. Dev
The POWER8™ processor: Designed for big data, analytics, and cloud environments
- Joshua Friedrich
- Hung Le
- et al.
- 2014
- ICICDT 2014
POWER8TM: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth
- Eric J. Fluhr
- Joshua Friedrich
- et al.
- 2014
- ISSCC 2014
Findings and considerations for I/O clock jitter on a source synchronous front side bus
- Daniel Dreps
- Len Daniels
- et al.
- 2012
- EPEPS 2012
A 2.6 mW/Gbps 12.5 Gbps RX with 8-Tap switched-capacitor DFE in 32 nm CMOS
- Thomas Toifl
- Christian Menolfi
- et al.
- 2012
- IEEE Journal of Solid-State Circuits