Publications

21 results for J. Kedzierski

Mobility and CMOS devices/circuits on sub-10nm (110) ultra thin body SOI
- - Huiling Shang
  - J. Rubino
  - et al.
- 2005
- VLSI Technology 2005
Quantum-based simulation analysis of scaling in ultrathin body device structures
- - Arvind Kumar
  - Jakub Kedzierski
  - et al.
- 2005
- IEEE Transactions on Electron Devices
Threshold voltage control in NiSi-Gated MOSFETs through SIIS
- - Jakub Kedzierski
  - Diane Boyd
  - et al.
- 2005
- IEEE Transactions on Electron Devices
Silicon device scaling to the sub-10-nm regime
- - Meikei Ieong
  - Bruce Doris
  - et al.
- 2004
- Science
Fabrication of metal gated FinFETs through complete gate silicidation with Ni
- - Jakub Kedzierski
  - Meikei Ieong
  - et al.
- 2004
- IEEE Transactions on Electron Devices
Scaling beyond conventional CMOS device
- - Meikei Ieong
  - Bruce Doris
  - et al.
- 2004
- ICSICT 2004
Advanced gate stacks with fully silicided (FUSI) gates and high-κ dielectrics: Enhanced performance at reduced gate leakage
- - E. Gusev
  - C. Cabral Jr.
  - et al.
- 2004
- IEDM 2004
Dual workfunction fully silicided metal gates
- - C. Cabral Jr.
  - J. Kedzierski
  - et al.
- 2004
- VLSI Technology 2004
Issues in NiSi-gated FDSOI device integration
- - Jakub Kedzierski
  - Diane Boyd
  - et al.
- 2003
- IEDM 2003
Threshold voltage control in NiSi-gated MOSFETs through silicidation induced impurity segregation (SIIS)
- - Jakub Kedzierski
  - Diane Boyd
  - et al.
- 2003
- IEDM 2003