A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS
- John F. Bulzacchelli
- Timothy O. Dickson
- et al.
- 2009
- ISSCC 2009
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28 results for Michael P. Beakes
A 7Gb/s 9.3mW 2-Tap current-integrating DFE receiver
- Matt Park
- John Bulzacchelli
- et al.
- 2007
- ISSCC 2007
A 10-Gb/s 5-tap DFE/4-tap FFE transceiver in 90-nm CMOS technology
- John F. Bulzacchelli
- Mounir Meghelli
- et al.
- 2006
- IEEE Journal of Solid-State Circuits
A 10Gb/s 5-tap-DFE/4-tap-FFE transceiver in 90nm CMOS
- M. Meghelli
- S. Rylov
- et al.
- 2006
- ISSCC 2006
A 6.4-Gb/s CMOS SerDes core with feed-forward and decision-feedback equalization
- Troy Beukema
- Michael Sorna
- et al.
- 2005
- IEEE Journal of Solid-State Circuits
A 10-Gb/s CMOS clock and data recovery circuit using a secondary delay-locked loop
- Woogeun Rhee
- Herschel Ainspan
- et al.
- 2003
- CICC 2003
A 2.3GSample/s 10-tap digital FIR filter for magnetic recording read channels
- S. Rylov
- A. Rylyakov
- et al.
- 2001
- ISSCC 2001
Single-chip 622-Mb/s SDH/SONET framer, digital cross-connect and add/drop multiplexer solution
- Peter H. Baechtold
- Michael P. Beakes
- et al.
- 2001
- IEEE Journal of Solid-State Circuits