Sub-300-ps CBL Circuits

This paper describes advanced charge-buffered-logic (CBL) circuits featuring double-poly self-alignment, a “free” epi-base lateral p-n-p (cutoff frequency = 300 MHz only), and deep trench isolation. Using 1.2-μm design rules and a modified push-pull output stage, a gate delay (fan-in = 3) of 278 ps was obtained at a dc current of 30 μA/gate. © 1989 IEEE