Self-Alignment of active Si Bridge using solder joint capillary forces

Transistor scaling is reaching its limit and is cost intensive, so gains in functionality increasingly rely on packaging advances. There is a growing need for heterogeneously integrated multi-chip packages to enhance bandwidth and minimize data transfer latency. To interconnect chips, assembly houses rely on high-density laminates, interposers or, more recently, silicon (Si) bridges [1]. Si bridges are particularly cost effective by constraining high density lines and spacing to the regions that require high connectivity. To further increase electrical performance characteristics such as power delivery and off-die parasitics, silicon bridges comprising thru-Si vias (TSVs) are key enabling structures [2]. For such TSV bearing dies, the need for interconnecting both faces places stringent controls on lateral alignment and interconnect height. Thermocompression bonding (TCB) has been favored thus far to accommodate such control, despite its lower throughput compared to mass reflow (MR). This paper proposes and demonstrates that, by thoroughly understanding the interrelationship between geometry and capillary forces, MR interconnection and the inherent auto-alignment of solder bumps can indeed be implemented for high throughput mass production of TSV-type Si bridge assemblies. We first present the fluidic simulation [3] of the vertical and lateral capillary forces as a function of solder thickness confined between two metallized pillars. This defined the required configurations for solder-on-pillar interconnection, namely volume, geometry, width and, above all, solder thickness. Subsequently, a design of experiments was conducted using the recommended configurations. The alignment effectiveness was measured using Si bridges on Si substrates that were assembled using an industrial pick and place complex and reflowed in a formic acid furnace. Alignment was assessed using top view infrared microscopy to measure x and y offset between metallic markers on the Si bridge underside surface and those on the Si substrate top surface. Preliminary proof of concept using a single interconnection at each corner demonstrated consistent alignment accuracy of under 2 µm with several trials achieving less than 1 micron offset. Mechanical profiling was used to determine z-tilt variation where tilt was consistently measured under 1 micron. Of particular interest was the effect of the number of TSV’s on the solder reflow self-alignment and therefore subsequent chip to bridge/substrate bonding integrity. As such, corner bump (1-4 bumps per corner) and full matrix pillar designs were compared. Results are used to validate bonding effectiveness on organic test vehicles. Finally, thermo-mechanical finite element analysis (FEM) simulations were conducted to understand the impact of the TSV-type Si bridge design, i.e. two-sided bonding, on interconnection stresses as compared to single-sided bonding of a standard Si bridge.

References

[1] Braunisch, Henning, Aleksandar Aleksov, Stefanie Lotz, et Johanna Swan. « High-Speed Performance of Silicon Bridge Die-to-Die Interconnects ». In 2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems, 95 98. San Jose, CA, USA: IEEE, 2011. https://doi.org/10.1109/EPEPS.2011.6100196.

[2] Elsherbini, A. A., S. M. Liff, et J. M. Swan. « Heterogeneous Integration Using Omni-Directional Interconnect Packaging ». In 2019 IEEE International Electron Devices Meeting (IEDM), 19.4.1-19.4.4. San Francisco, CA, USA: IEEE, 2019. https://doi.org/10.1109/IEDM19573.2019.8993659.

[3] Yves Martin, Jae-Woong Nah, Swetha Kamlapurkar, Sebastian Engelmann, et Tymon Barwicz. « Toward High-Yield 3D Self-Alignment of Flip-Chip Assemblies via Solder Surface Tension ». In 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), 588 94, 2016. https://doi.org/10.1109/ECTC.2016.239.