Conference paper
Dual work function metal gate CMOS using CVD metal electrodes
V. Narayanan, A.C. Callegari, et al.
VLSI Technology 2004
Surface potential profiles of the junction area of a cleaved n-Si (100) Hf O2 p+ -polycrystalline silicon (poly-Si) gate stack reveal a dipole potential in the oxide, hole trapping at the Hf O2 /poly-Si interface, with the Fermi level ∼0.4 eV below the Si conduction bandedge and enhanced and inhomogeneous hole depletion in the p+ -poly-Si. The dipole accounts for band bending reduction in the n-Si and is consistent with flatband voltage shifts reported for similar gate stacks. © 2005 American Institute of Physics.
V. Narayanan, A.C. Callegari, et al.
VLSI Technology 2004
R. Ludeke, E. Cartier
Applied Physics Letters
S. Zafar, M. Yang, et al.
VLSI Technology 2005
J.-P. Han, E.M. Vogel, et al.
IEEE Electron Device Letters