Conference paper
NanoStack Transistor Architecture for CMOS 7A Node and Beyond
S. Reboh, C. Zhang, et al.
VLSI Technology and Circuits 2025
Surface potential profiles of the junction area of a cleaved n-Si (100) Hf O2 p+ -polycrystalline silicon (poly-Si) gate stack reveal a dipole potential in the oxide, hole trapping at the Hf O2 /poly-Si interface, with the Fermi level ∼0.4 eV below the Si conduction bandedge and enhanced and inhomogeneous hole depletion in the p+ -poly-Si. The dipole accounts for band bending reduction in the n-Si and is consistent with flatband voltage shifts reported for similar gate stacks. © 2005 American Institute of Physics.
S. Reboh, C. Zhang, et al.
VLSI Technology and Circuits 2025
M. Copel, S. Guha, et al.
Applied Physics Letters
C. Cabral Jr., C. Lavoie, et al.
JES
A.B. McLean, R. Ludeke
Physical Review B