Dual work function metal gate CMOS using CVD metal electrodes
V. Narayanan, A.C. Callegari, et al.
VLSI Technology 2004
Surface potential profiles of the junction area of a cleaved n-Si (100) Hf O2 p+ -polycrystalline silicon (poly-Si) gate stack reveal a dipole potential in the oxide, hole trapping at the Hf O2 /poly-Si interface, with the Fermi level ∼0.4 eV below the Si conduction bandedge and enhanced and inhomogeneous hole depletion in the p+ -poly-Si. The dipole accounts for band bending reduction in the n-Si and is consistent with flatband voltage shifts reported for similar gate stacks. © 2005 American Institute of Physics.
V. Narayanan, A.C. Callegari, et al.
VLSI Technology 2004
D.N. McIlroy, D. Heskett, et al.
Physical Review B
E.J. Preisler, S. Guha, et al.
Applied Physics Letters
R. Ludeke, P. Lysaght, et al.
Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures