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ISSCC 2014
This work describes the design and characterization of a unique circuit which can be easily integrated into a microprocessor product in order to determine the degradation of circuit speed caused by negative bias temperature instability (NBTI)-induced shifts under typical product operating voltage and temperature. These data can subsequently be compared to models for circuit degradation in order to assess the validity of the models. ©2008 IEEE.
Eric J. Fluhr, Joshua Friedrich, et al.
ISSCC 2014
Shu-Jen Han, Dharmendar Reddy, et al.
ACS Nano
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IRPS 2018
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ISDRS 2003